A serial data channel is used to transport binary information (e.g., in single ended or differential format) one bit at a time. FIG. 1 shows an exemplary depiction of a receive channel that includes a serial data channel 100. The serial data channel 100 is typically implemented with copper or fiber optic cabling (which is typically attached at an industry standard connector 120 (e.g., a BNC connector) and is coupled to a serial-to-parallel conversion block 101. The serial-to-parallel conversion block 101 effectively converts a number of bits received from the serial data channel 100 into a word of data of width X that is presented at output 105. The serial-to-parallel conversion block also includes a clock output 106. The clock provided at output 106 typically has a frequency that is equal to the frequency at which new words are presented at output 105 (i.e., CLK/X where the frequency of CLK corresponds to the baud rate of the serial data channel).
Other functions that may be performed by the serial-to-parallel conversion block 101 include optical-to-electrical conversion (O/E), amplification and clock extraction. O/E is used if the serial data channel 100 is actually implemented with an optical transport mechanism. Amplification is used when the serial data channel 100 traverses long distances and the transported signals are weakened as a consequence. Clock extraction is the derivation of the frequency of the clock used to transmit data onto the serial data channel from the data that is received on the serial data channel. A photodetector is often used for O/E, amplifier circuitry is often used for amplification; and, phase locked loop circuitry is often used for clock extraction.
An alignment key synchronization block 102 is used to synchronize or “align” the stream of 1s and 0s received on the serial data channel 100. Here, data carried over the serial data channel 100 is viewed as being organized into a series of words (e.g., where each word is a ten bit block of data). The alignment key synchronization block 102 is responsible for deciding where the boundaries of neighboring words reside in the stream of 1s and 0s that are received from the serial data channel 100. Typically a specific word pattern (e.g., a specific 10 bit word pattern), referred to as an alignment key, is embedded into the serial data channel's data stream at the transmitting source.
By looking for and recognizing the presence of the alignment key, the alignment key synchronization block 102 is able to precisely determine the word boundaries within the serial data channel's 100 data stream. In a typical embodiment, the alignment key found output 109 triggers to an active state when the alignment key is discovered in the data stream; and, subsequently, correctly aligned words from the serial data channel's data stream are provided at output 107. Thus, for example, if the serial data stream is organized into ten bit words, Y=10 or some integer multiple thereof. Moreover, as just mentioned above, the data is properly aligned at output 107 such that the least significant bit and the most significant bit of the Y wide output correspond to word “endpoint” bits within the serial data stream. The strobe output 108 provides a clock that times the presence of each new output word presented at output 107.
A decoder 103 decodes the aligned words that are presented at the alignment key synchronization block data output 107 into smaller words of data that correspond to the actual, substantive data that the serial data channel is used to transport. Here, on the transmit side, the actual substantive data that is to be transported by the serial data channel is first encoded in order to prevent data corruption in cases of long run lengths of the same binary value (e.g., a long run length of 1s or a long run length of 0s). The decoder 103 reverses the encoding process. Typically, a decoded word that corresponds to actual substantive data is provided at output 104 for each aligned word provided at the alignment key synchronization block output 107. Owing to the nature of encoding schemes, some inefficiency is associated with the decoding process in that more bits are needed to transport encoded data (as compared to un-encoded data). As such, the per word width at output 104 is less than the per word width at output 107 (i.e., Y>Z).
Note that, in cases where the serial-to-parallel block 101 does not form words of the same size as the words that are formed into the serial data stream, the alignment key synchronization block 102 also performs some degree of parallel word size translation from an input word of width X to an output word of width Y. Typically Y is greater than X. In cases where the output word width Y is an integer multiple of the input word width X (e.g., X=4 and Y=8), the parallel word size translation is straightforward to design. However, in cases where the output word width Y is not an integer multiple of the input word width X (e.g., X=4 and Y=10), the parallel word size translation can be much more complicated to design and, to the knowledge of the Applicants, has heretofore required the use of dual edge triggered flip flops.